This application claims the priority benefit of Taiwan application serial no. 89126178, filed Dec. 8, 2000.
1. Field of Invention
The present invention relates to a method of manufacturing semiconductor memory. More particularly, the present invention relates to a method of manufacturing flash memory.
2. Description of Related Art
Flash memory is a type of electrically erasable programmable read-only-memory (EEPROM). Not only can data be written into, read and erased from a flash memory, programmed data can be retained after power is cut. Hence, flash memory is a versatile electronic component that is widely used inside personal computers and electronic equipment.
The floating gate and the control gate of a typical flash memory are formed using doped polysilicon. During memory programming, electrons injected into the floating gate are evenly distributed over the entire polysilicon floating gate layer. However, if the tunneling layer underneath the polysilicon floating gate layer is defective, electrons may leak out, leading to device reliability problem.
FIG. 1 is a schematic cross-sectional view of a recently developed conventional flash memory unit. As shown in FIG. 1, the flash memory has a floating gate 104 made of silicon nitride and a control gate 108 made of polysilicon. When a voltage is applied to the control gate 108 and a source region 110 during programming, electrons will be injected from the channel region close to a drain region 112 into the floating gate 104. Since silicon nitride has good electron trapping capacity, electrons injected into the silicon nitride floating gate 104 will not be evenly distributed across the entire floating gate 104. Instead, the electrons may be trapped within a localized region following a Gaussian distribution. Because the electrons injected into the floating gate 104 are mainly collected in a localized region, this type of configuration is intrinsically less sensitive to defects in the tunneling oxide layer 102 and current leak occurs less frequently.
Another advantage of using silicon nitride to fabricate the floating gate is that electrons will only concentrate in the floating gate 104 region close to the drain 112 during programming. Voltages can be applied to the control gate 108 and the source/drain regions 110 and 112 at both ends of the control gate 108 during programming. Ultimately, a Gaussian distribution of electrons is produced in the silicon nitride floating gate 104. Hence, by changing the voltages applied to the control gate 108 and the source/drain regions 110 and 112 on each side of the control gate, electrons may be channeled into two localized regions, each having a Gaussian distribution, in the floating gate, or channeled into a single localized region with a Gaussian distribution in the floating gate, or entirely prevented from going into the floating gate and thus forming an electron-free region. Therefore, a single memory cell can have four states when silicon nitride is used to fabricate the floating gate of a flash memory unit. In other words, a flash memory cell capable of holding altogether two bits of data is produced.
The conventional process of manufacturing the 1-cell-2-bit flash memory includes placing a silicon wafer 100 into a pipe furnace to form a tunneling oxide layer 102 over the wafer 100. Thereafter, silicon nitride is deposited over the tunneling oxide layer 102 by vapor deposition to form a floating gate layer 104. The wafer 100 is again put inside the pipe furnace and silicon oxide is deposited over the floating gate layer 104 to form a dielectric layer 106. Finally, a control gate layer 108 is formed over the dielectric layer 106 by chemical vapor deposition.
In the aforementioned method, the wafer must be thoroughly cleaned to remove contaminant particles after forming the tunneling oxide layer before passing the wafer into a chemical vapor deposition chamber to form the silicon nitride floating gate, and after forming the silicon oxide dielectric layer before passing the wafer into the chemical vapor deposition chamber to form the control gate. Wafer cleaning not only increases production cost, but also extends production time and lowers productivity.
Furthermore, the tunneling oxide layer, the silicon nitride floating gate, the oxide layer and the control gate are formed in different processing stations. Since suitable vacuum conditions must be established inside a reaction chamber before carrying out each processing step, a lot of setup time is wasted and hence productivity is lowered.
In addition, since the tunneling oxide layer, the silicon nitride floating gate, the oxide layer and the control gate are formed in different processing stations, the silicon wafer is likely to be exposed to the surroundings between each processing step. Due to exposure, the chance of engendering defects is greater. Moreover, each processing station will process a batch of wafers at a time. If there are any errors in processing, the entire batch of wafers may have to be reworked or discarded.
Accordingly, one object of the present invention is to provide a method of manufacturing flash memory capable of reducing the time required to prepare the processing station for forming the various layers in the flash memory and hence increasing productivity.
A second object of the invention is to provide a method of manufacturing flash memory capable of forming the tunneling oxide layer, the silicon nitride floating gate, the oxide layer and the control gate of the flash memory without breaking the vacuum created inside a reaction chamber between each step.
A third object of the invention is to provide a method of manufacturing flash memory capable of eliminating the cleaning operation after each of the layers, including the tunneling oxide layer, the silicon nitride floating gate, the oxide layer and the control gate, is formed.
A fourth object of the invention is to provide a method of manufacturing flash memory capable of reducing defects or defect density so that yield and reliability of flash memory are increased.
A fifth object of the invention is to provide a method of manufacturing flash memory capable of reducing the amount of rework or scrap so that production cost is lowered.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of manufacturing flash memory. The method uses a single wafer consecutive processing system. A single wafer is placed inside a station for chemical vapor deposition. The reaction station has a plurality of reaction chambers. Each layer of the flash memory, including the tunneling oxide layer, the silicon nitride floating gate, the oxide layer and the control gate, is formed in a different reaction chamber.
According to the embodiment of this invention, each of the layers, including the tunneling oxide layer, the silicon nitride floating gate, the oxide layer and the control gate, is formed in one of the reaction chambers of the chemical vapor deposition station. The types of chemical vapor deposition that can be performed by the station include low-pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), sub-atmospheric pressure chemical vapor deposition (SACVD), plasma-enhanced chemical vapor deposition (PECVD) and rapid thermal chemical vapor deposition (RTCVD).
The tunneling oxide layer, the silicon nitride floating gate, the oxide layer and the control gate are all formed inside the chemical vapor deposition station. Since there is no need to transfer the silicon wafer from one station to another, time setting up a station is saved and hence productivity is increased.
Since the tunneling oxide layer, the silicon nitride floating gate, the oxide layer and the control gate are all formed inside an sealed reaction chamber, there is no need to break the vacuum inside the chamber between each processing step. With less contact with environmental contaminants, fewer defects will form in the deposited films. Hence, product yield and device reliability is improved.
In addition, the various layers in the flash memory are formed using a single wafer consecutive system. If any abnormal condition is found in a particular wafer, the processing step can be terminated immediately. Only one silicon wafer needs to be scrapped or reworked at a time. Hence, compared with a conventional batch processing method, the invention is capable of reducing the quantity of defective products.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.